1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement in alignment of semiconductor device formed by overlaying a plurality of layers.
2. Description of the Background Art
Recently, with high integration of elements, the design rule becomes smaller and a manufacturing process becomes more complicated with planarization technique and use of new materials. Since miniaturization of contact holes and interconnections requires higher precision in alignment of the contact holes and the interconnections and therefore a higher alignment technique is needed.
To form contact holes and interconnections, an exposure device termed a stepper is used. A mask pattern projected by reducing projection lens system is repeatedly exposed while moving in an XY direction, to form a plurality of circuit patterns on a whole surface of a semiconductor substrate.
FIG. 41 schematically shows an operation of the stepper in a lithography process. As shown in FIG. 41, a plurality of exposure regions ER each of which is projected by one exposure are formed on a whole surface of a semiconductor substrate SB. A plurality of exposures are made on each exposure region ER, overlaying different patterns, to form a semiconductor device.
In overlay of patterns, an alignment mark for alignment is needed and after overlay, an overlay check mark is needed to check if the overlay is made properly. Each exposure region ER is provided with these marks.
In general, most part of the exposure region is an element formation region in which a plurality of semiconductor elements are formed and the rest blank part is used for forming the alignment mark and the overlay check mark. FIG. 42 shows a schematic structure of the exposure region ER. In FIG. 42, two element formation regions SR are placed at an interval and an overlay check mark OLM1 and an alignment mark ALM1 are provided in a blank portion BR between the two element formation regions SR and overlay check marks OLM2 to OLM5 are provided in the four corners of a blank portion BR surrounding the two element formation regions SR. Further, between the overlay check mark OLM2 and OLM3 provided is an alignment mark ALM2.
Though the five overlay check marks and the two alignment marks are shown in FIG. 42, the number of either mark is not limited to the above numbers. Further, since the present invention can be applied to both the alignment mark and the overlay check mark, the alignment mark and the overlay check mark are not distinguished from each other and both marks are generally referred to as position check mark in the discussion hereinafter (including discussion of the preferred embodiment of the invention).
FIG. 43 is a plan view of a position check mark MK1 as an example of position check mark. As shown in FIG. 43, the position check mark MK1 consists of a plurality of mark structures 10 which are each of elongated shape having a predetermined length and arranged in parallel at intervals.
FIG. 44 is a cross sectional view taken along the line Axe2x80x94A of FIG. 43. As shown in FIG. 44, the mark structure 10 consists of a gate oxide film 102 (a thermal oxide film having a thickness of about 10 nm) formed on a silicon substrate 101, a gate wiring layer 103 formed on the gate oxide film 102, an insulating film 104 formed on the gate wiring layer 103 and a sidewall 105 formed in contact with side surfaces of the insulating film 104, the gate wiring layer 103 and the gate oxide film 102.
The gate wiring layer 103 is a polycide consisting of two layers, i.e., a doped polysilicon layer 1031 having a thickness of, e.g., 100 nm and a tungsten silicide (WSi) layer 1032 having a thickness of 100 nm. The insulating film 104 is made of a TEOS (Tetra Ethyl Orthosilicate) oxide film having a thickness of, e.g., about 200 nm, and the sidewall 105 is made of a TEOS oxide film having a thickness of, e.g., 50 nm.
A stopper insulating film 106 is so provided as to cover an arrangement of mark structures 10 each having the above structure. The stopper insulating film 106 is a translucent silicon nitride film having a thickness of 50 nm. An interlayer insulating film 107 is formed of a TEOS oxide film having a thickness of e.g., 500 nm, covering the stopper insulating film 106, and its outermost surface is planarized by CMP (Chemical Mechanical Polishing).
On the interlayer insulating film 107, an opaque bit line layer 109 is formed as a polycide of a doped polysilicon layer 1091 having a thickness of, e.g., 100 nm and a tungsten silicide (WSi) layer 1092 having a thickness of 100 nm.
A mark structure 10 substantially has the same structure as a gate of a MOS transistor, for it is formed through the same process steps as the gate of the MOS transistor when the MOS transistor is formed as one of semiconductor elements in the element formation region SR of FIG. 42, and this is a technique for preventing an increase in the number of process steps by steps dedicated to formation of the position check mark MK1. Therefore, the mark structure 10 is a dummy gate and has no function of gate.
The stopper insulating film 106 serves as an etching stopper in formation of the contact hole penetrating the interlayer insulating film 107 to reach the semiconductor substrate 101 in the element formation region SR in a self-align manner, and is also provided in formation of the MOS transistor in the element formation region SR.
The interlayer insulating film 107 is also formed in the element formation region SR, and on the interlayer insulating film 107 planarized by CMP, the bit line layer 109 is formed.
Thus, since the mark structure 10 is formed in the same manner as the gate of the MOS transistor and on the mark structure 10, the opaque bit line layer 109 is formed with the planarized interlayer insulating film 107 interposed therebetween, the following problem arises.
When the bit line layer 109 is patterned to form a predetermined bit-line pattern, a mask pattern of the stepper is aligned by using the position check mark MK1 consisting of the mark structures 10. After the bit-line pattern is formed, the position check mark MK1 is used to check if the pattern is overlaid on a proper position. In both cases, since the mark structures 10 are measured through the opaque bit line layer 109 and the bit line layer 109 hardly transmits the visible light used in the measurement, the level difference of the mark structure 10 can hardly be measured. Further, since the interlayer insulating film 107 is planarized, disadvantageously, the existences of the mark structures 10 can not be seen from the interlayer insulating film 107.
Furthermore, affected by the translucent stopper insulating film 106, the intensity of the visible light used for the measurement is lowered and the contrast is worsened, disadvantageously not to allow a measurement with high precision.
Though the position check mark MK1 consisting of arranged mark structures 10 each of which substantially has the same structure as the gate of the MOS transistor has been discussed above, the structure of the mark structure is not limited to the gate structure.
FIG. 45 is a plan view of a position check mark MK2 as an example of a mark. As shown in FIG. 45, the position check mark MK2 consists of elongated openings having a predetermined length arranged in parallel at intervals on an oxide film 734.
FIG. 46 is a cross sectional view taken along the line Bxe2x80x94B of FIG. 45. As shown in FIG. 46, the position check mark MK2 consists of openings OP where an interlayer insulating film 717 formed on the silicon substrate 101 is selectively removed in a rectangular shape to partially expose the silicon substrate 101 and a doped polysilicon layer 733 buried in the openings OP, having a thickness of 50 nm, and the oxide film 734 formed on the doped polysilicon layer 733. Further, an insulating film 726 is formed between a main surface of the interlayer insulating film 717 and the doped polysilicon layer 733. The oxide film 734 does not completely fill the opening and an opening 748 corresponding to the opening OP is formed. Further, sidewalls 735 are formed on walls of the opening 748.
The interlayer insulating film 717 is formed of a TEOS oxide film having a thickness of, e.g., 500 nm and its outermost surface is planarized by CMP. The insulating film 726 is a translucent silicon nitride film having a thickness of 50 nm and the oxide film 734 is a BPTEOS (boro-phospho TEOS) film having a thickness of 600 nm. The sidewall 735 is formed of a doped polysilicon having a thickness of, e.g., 50 nm.
Herein, a stacked capacitor SC corresponding to the position check mark MK2 in the element formation region SR of FIG. 42 will be discussed with reference to FIG. 47. As shown in FIG. 47, the stacked capacitor SC consists of a contact hole 708 selectively so formed as to penetrate the interlayer insulating film 717 and the insulating film 726, a bottom storage node 733 so provided as to fill the contact hole 708, a storage node core 734 formed on the bottom storage node 733 and the sidewall 735 so formed as to surround the storage node core 734.
Thus, the insulating film 726, the doped polysilicon layer 733, the oxide film 734 and the sidewall 735 of the position check mark MK2 correspond to the insulating film 726, the bottom storage node 733, the storage node core 734 and the sidewall 735 of the stacked capacitor SC and formed through the same steps, respectively. Further, though the opening OP of the position check mark MK2 is formed through the same step as the contact hole 708 of the stacked capacitor SC, these are greatly different in size, specifically, in that the contact hole 708 has an opening size of, e.g., about 0.2 xcexcm and the opening OP has a size of, e.g., 2 xcexcm or larger.
Now, existence of the sidewall 735 formed on the wall of the opening 748 of the position check mark MK2 causes a problem. In the stacked capacitor SC, the storage node core 734 is not needed, and the storage node core 734 is removed by selective etching using, e.g., vapor hydrofluoric acid, a dielectric film is formed along an outline of the bottom storage node 733 and the sidewall 735 and a counter electrode to the bottom storage node 733, termed cell plate, is formed along an outline of the dielectric film, to complete a storage node.
When the storage node core 734 is removed, the oxide film 734 of the position check mark MK2 is also removed. With this, when the sidewall 735 is removed off and the removed thing adheres to the element formation region SR, this develops a short circuit of the elements, disadvantageously resulting in defectives and remarked deterioration in manufacturing process yield.
Thus, in the method of manufacturing a semiconductor device in the background art, the alignment mark and the overlay check mark can not be measured or can be measured with much lower precision in the lithography process. In some structures of mark, when the mark is formed concurrently with the semiconductor device, unnecessary structure for the mark is also formed attendantly and this unnecessary structure becomes an extraneous matter in the manufacturing process of the semiconductor device, resulting in defectives of the semiconductor device and deterioration in manufacturing process yield.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of the plurality of layers, where the semiconductor element has a first wiring layer; an interlayer insulating film covering the first wiring layer; and a second wiring layer formed on the interlayer insulating film, and where the position check mark has an opening provided by selectively removing the interlayer insulating film; a mark structure formed in the opening, having the first wiring layer; and the second wiring layer placed along an outline of the mark structure.
According to a second aspect of the present invention, the second wiring layer is opaque or translucent, and projection and depression of the second wiring layer covering the mark structure are measured as a mark for position check when the second wiring layer is patterned.
According to a third aspect of the present invention, the semiconductor element includes a MOS transistor, the first wiring layer is a gate wiring layer, and the mark structure has the same structure as a gate of the MOS transistor.
According to a fourth aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of the plurality of layers, where the semiconductor element has a first wiring layer; a first interlayer insulating film covering the first wiring layer; a second interlayer insulating film formed on the first interlayer insulating film; and a second wiring layer formed at least on the second interlayer insulating film, and where the position check mark has an opening provided by selectively removing the first interlayer insulating film; a mark structure formed in the opening, having the first wiring layer; the second interlayer insulating film provided extending from on the first interlayer insulating film to on the mark structure, having an outline with projection and depression corresponding to an outline of the mark structure; and the second wiring layer placed along the outline of the second interlayer insulating film.
According to a fifth aspect of the present invention, the second wiring layer is opaque or translucent, and projection and depression of the second wiring layer constituting the position check mark are measured as a mark for position check when the second wiring layer is patterned.
According to a sixth aspect of the present invention, the semiconductor element is a memory element including a MOS transistor and a capacitor electrically connected to the MOS transistor, the first wiring layer is a gate wiring layer, the mark structure has the same structure of a gate of the MOS transistor, and the second wiring layer is a cell plate of the capacitor.
According to a seventh aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of the plurality of layers, where the semiconductor element has an interlayer insulating film formed on the semiconductor substrate; a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate; and a first conductive film placed to fill at least the contact hole, and where the position check mark has a plurality of mark holes so formed as to penetrate the interlayer insulating film; and a second conductive film so placed as to fill at least the plurality of mark holes.
According to an eighth aspect of the present invention, the semiconductor element is a capacitor, the first conductive film is a storage node, the storage node is so provided as to protrude from the contact hole, the capacitor further has a first sidewall which is conductive and extends perpendicularly to the interlayer insulating film, surrounding a protruding portion of the storage node, the second conductive film which is part of a conductive film including the first conductive film, and is so formed on the interlayer insulating film as to fill the plurality of mark holes and extend over the plurality of mark holes, and the position check mark further has a second sidewall which is conductive, has almost the same structure as the first sidewall and extends perpendicularly to the interlayer insulating film, surrounding an outer peripheral edge portion of the second conductive film.
According to a ninth aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of the plurality of layers, where the semiconductor element has an interlayer insulating film formed on the semiconductor substrate; a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate; a plug which is conductive and fills the contact hole; a barrier metal layer so provided as to cover the contact hole and to be electrically connected to the plug; and a conductive film formed on the barrier metal layer, and where the position check mark has a plurality of mark holes so formed as to penetrate the interlayer insulating film; a recess plug which is conductive and provided so that its one end portion on a side opposite to the semiconductor substrate is recessed in the plurality of mark holes; the barrier metal layer so provided as to cover the plurality of mark holes and to be electrically connected to the recess plug; and the conductive film formed on the barrier metal layer.
According to a tenth aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of the plurality of layers, where the semiconductor element has an interlayer insulating film formed on the semiconductor substrate; a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate; a plug which is conductive and fills the contact hole; a barrier metal layer so provided as to cover the contact hole and to be electrically connected to the plug; and a conductive film formed on the barrier metal layer, and where the position check mark has a recess region in which a determined region of the interlayer insulating film is recessed; a plurality of mark holes so formed as to penetrate the interlayer insulating film in the recess region; a protrusion plug which is conductive and provided so that its one end portion on a side opposite to the semiconductor substrate protrudes from the plurality of mark holes; the barrier metal layer so provided as to cover the plurality of mark holes and to be electrically connected to the protrusion plug; and the conductive film formed on the barrier metal layer.
According to an eleventh aspect of the present invention, the opening size of each of the plurality of mark holes ranges from almost as large as that of the contact hole to almost twice.
According to a twelfth aspect of the present invention, the plurality of mark holes are formed through the same process as the contact hole.
The present invention is directed to a method of manufacturing a semiconductor device which comprises a semiconductor element formed on a semiconductor substrate by overlaying a plurality of patterned layers and a position check mark used for overlay of the plurality of layers. According to a thirteenth aspect of the present invention, the method comprises the steps of: (a) forming a first wiring layer on a first region in which the semiconductor element is formed on the semiconductor substrate and a second region which surrounds the first region with an insulating film interposed therebetween; (b) forming an upper oxide film and a sidewall oxide film in an upper portion and on a side surface of the first wiring layer, respectively; (c) so forming a nitride film as to cover the upper oxide film and the sidewall oxide film; (d) so forming an interlayer insulating film as to cover the first and second regions; (e) so forming a contact hole in a self-align manner as to penetrate the interlayer insulating film of the first region to reach at least the nitride film extending from on the sidewall oxide film to on the semiconductor substrate, and selectively removing the interlayer insulating film of the second region in accordance with a formation region of the position check mark to form an opening, thereby exposing the nitride film; (f) removing the nitride film exposing on a bottom of the contact hole and the opening to extend the contact hole to the semiconductor substrate and to leave a mark structure consisting of the insulating film, the first wiring layer, the upper oxide film and the side wall oxide film formed in the opening in the step (a) and (b); and (g) so forming a second wiring layer as to cover the first and second regions, burying the second wiring layer in the contact hole, and placing the second wiring layer along an outline of the mark structure at the same time, and in the method of the thirteenth aspect, the position check mark is formed in the steps (f) and (g).
According to a fourteenth aspect of the present invention, the method comprises the steps of: (a) forming a first wiring layer on a first region in which the semiconductor element is formed on the semiconductor substrate and a second region which surrounds the first region with an insulating film interposed therebetween; (b) forming an upper oxide film in an upper portion of the first wiring layer; (c) forming a sidewall oxide film on side surfaces of the first wiring layer and the upper oxide film in the first region; (d) so forming a nitride film as to cover the upper oxide film and the sidewall oxide film in the first region and the first wiring layer and the upper oxide film in the second region; (e) selectively removing the nitride film covering the first wiring layer and the upper oxide film in the second region to form a sidewall nitride film; (f) so forming an interlayer insulating film as to cover the first and second regions; (g) so forming a contact hole in a self-align manner as to penetrate the interlayer insulating film of the first region to reach at least the nitride film extending from on the sidewall oxide film to on the semiconductor substrate, selectively removing the interlayer insulating film of the second region in accordance with a formation region of the position check mark to provide an opening, exposing the nitride film, and removing the upper oxide film; (h) removing the nitride film exposing on bottoms of the contact hole and the opening to extend the contact hole to the semiconductor substrate and to leave a mark structure consisting of the insulating film, the first wiring layer and the side wall nitride film formed in the opening in the step (a), (b) and (e); and (i) so forming a second wiring layer as to cover the first and second regions, burying the second wiring layer in the contact hole, and placing the second wiring layer along an outline of the mark structure exposed in the opening at the same time, and in the method of the fourteenth aspect, the position check mark is formed in the steps (h) and (i).
According to a fifteenth aspect of the present invention, the method comprises the steps of: (a) so forming an interlayer insulating film as to cover a first region in which the semiconductor element is formed on the semiconductor substrate and a second region which surrounds the first region; (b) providing a contact hole which penetrates the interlayer insulating film of the first region to reach the semiconductor substrate, and forming a plurality of mark holes which penetrate the interlayer insulating film of the second region to reach the semiconductor substrate; (c) so forming a conductive film on the interlayer insulating film on the first and second regions as to fill the contact hole and the plurality of mark holes; (d) forming an insulating film on the conductive film; (e) so selectively removing the insulating film and the conductive film as to leave the insulating film on the contact hole and leave the conductive film on the plurality of mark holes and on between the plurality of mark holes; (f) forming sidewalls which are conductive on side surfaces of the conductive film and the insulating film on the contact hole and side surfaces of the conductive film and the insulating film on the plurality of mark holes and on between the plurality of mark holes; and (g) removing the insulating film, and in the method of the fifteenth aspect, the position check mark is formed in the steps (b) to (g).
According to a sixteenth aspect of the present invention, the method comprises the steps of: (a) so forming an interlayer insulating film as to cover a first region in which the semiconductor element is formed on the semiconductor substrate and a second region which surrounds the first region; (b) providing a contact hole which penetrates the interlayer insulating film of the first region to reach the semiconductor substrate, and forming a plurality of mark holes which penetrate the interlayer insulating film of the second region to reach the semiconductor substrate; (c) filling the contact hole and the plurality of mark holes with a plug which is conductive; (d) partially removing the plug so that one end portion of the plug in the plurality of mark holes on a side opposite to the semiconductor substrate is recessed in the plurality of mark holes, to form a recess plug; and (e) so placing a barrier metal layer as to cover the first and second regions and to be electrically connected to the plug in the contact hole and the recess plug in the plurality of mark holes, and then forming a conductive film on the barrier metal layer, and in the method of the sixteenth aspect, the position check mark is formed in the steps (b) to (e).
According to a seventeenth aspect of the present invention, the method comprises the steps of: (a) so forming an interlayer insulating film as to cover a first region in which the semiconductor element is formed on the semiconductor substrate and a second region which surrounds the first region; (b) providing a contact hole which penetrates the interlayer insulating film of the first region to reach the semiconductor substrate, and forming a plurality of mark holes which penetrate the interlayer insulating film of the second region to reach the semiconductor substrate; (c) filling the contact hole and the plurality of mark holes with a plug which is conductive; (d) recessing a predetermined region in the interlayer insulating film of the second region in which the plurality of mark holes are formed to form a recess region and protruding one end portion of the plug on a side opposite to the semiconductor substrate from the plurality of mark holes, to form a protrusion plug; and (e) so placing a barrier metal layer as to cover the first and second regions and to be electrically connected to the plug in the contact hole and the protrusion plug protruding from the plurality of mark holes, and then forming a conductive film on the barrier metal layer, and in the method of the seventeenth aspect, the position check mark is formed in the steps (b) to (e).
According to an eighteenth aspect of the present invention, the step (b) includes a step of setting the opening size of each of the plurality of mark holes from almost as large as that of the contact hole to almost twice.
According to a nineteenth aspect of the present invention, the step of forming the interlayer insulating film includes a step of planarizing the interlayer insulating film by CMP (Chemical Mechanical Polishing).
In the semiconductor device of the first aspect of the present invention, since the second wiring layer is placed along an outline of the mark structure, the level difference of the mark structure is left as projection and depression of the second wiring layer and the mark structure can be measured indirectly through the second wiring layer. Therefore, for example, when the second wiring layer is patterned to form a predetermined interconnection pattern, the mark structure is measured indirectly through the second wiring layer to make an alignment of mask pattern of the stepper, and after the predetermined interconnection pattern is formed, the position check mark is used to check if the pattern is overlaid on a proper position.
In the semiconductor device of the second aspect of the present invention, if the second wiring layer is opaque or translucent, when the second wiring layer is patterned, by measuring the projection and depression of the second wiring layer covering the mark structure as the mark structure, the mark structure can be measured indirectly through the second wiring layer to avoid defectiveness such as misalignment.
In the semiconductor device of the third aspect of the present invention, since the mark structure has the same structure as the gate of the MOS transistor, the mark structure can be formed in the process of manufacturing the MOS transistor and a whole manufacturing process is simplified as compared with a case where a dedicated process of forming the position check mark is established.
In the semiconductor device of the fourth aspect of the present invention, since the position check mark has the second interlayer insulating film having an outline with projection and depression corresponding to the outline of the mark structure and the second wiring layer placed along the outline of the second interlayer insulating film, the level difference of the mark structure is left as the level difference in projection and depression of the second interlayer insulating film and further as the level difference in projection and depression of the second wiring layer, and the mark structure can be measured indirectly through the second wiring layer. Therefore, for example, when the second wiring layer is patterned to form a predetermined interconnection pattern, the mark structure is measured indirectly through the second wiring layer to make an alignment of mask pattern of the stepper, and after the predetermined interconnection pattern is formed, the position check mark is used to check if the pattern is overlaid on a proper position.
In the semiconductor device of the fifth aspect of the present invention, if the second wiring layer is opaque or translucent, when the second wiring layer is patterned, by measuring the projection and depression of the second wiring layer covering the mark structure as the mark structure, the mark structure can be measured indirectly through the second wiring layer to avoid defectiveness such as misalignment.
In the semiconductor device of the sixth aspect of the present invention, since the mark structure has the same structure as the gate of the MOS transistor and the second wiring layer has the same structure as the cell plate of the capacitor, a manufacturing process is simplified as compared with a case where a dedicated process of forming the position check mark is established.
In the semiconductor device of the seventh aspect of the present invention, the position check mark has a plurality of mark holes so formed as to penetrate the interlayer insulating film and the second conductive film so formed as to fill at least a plurality of mark holes, the position check mark is a hole-shaped mark and suitable for formation of a semiconductor element having the first conductive film in the contact hole. Specifically, when a hole-shaped pattern is overlaid by using a hole-shaped mark, an influence of coma aberration can be reduced to lessen misalignment of the pattern as compared with the case where alignment of the hole-shaped pattern is made by using the line-shaped mark.
In the semiconductor device of the eighth aspect of the present invention, when the semiconductor element is a capacitor, by setting the opening size of the mark hole almost as large as that of the contact hole, the same structure as the capacitor is formed on an upper portion of the mark hole through the process of forming the capacitor. Specifically, in the capacitor having a structure in which a protruding portion of the storage node is surrounded by the first sidewall, since the position check mark is formed through the same step as the first sidewall to have the second sidewall which is conductive and extends perpendicularly to the interlayer insulating film, surrounding an outer peripheral edge portion of the second conductive film, the second conductive film and the second sidewall are united and when an insulating film needed only in the manufacturing process is formed in a region defined by the second conductive film and the second sidewall, even if the insulating film is removed, there arises no phenomenon where the second sidewall is removed, floating, for example, in an etchant solution, and it is possible to prevent short circuit of the semiconductor element by the second sidewall, which leads to defectiveness and deterioration in manufacturing process yield.
In the semiconductor device of the ninth aspect of the present invention, since the position check mark has a plurality of mark holes so formed as to penetrate the interlayer insulating film and a conductive recess plug formed so that its end portion on a side opposite to the semiconductor substrate may be recessed in the plurality of mark holes and the barrier metal layer is so formed as to be electrically connected to the recess plug, a surface of the barrier metal corresponding to the positions of the mark holes has depressions and further the conductive film thereon has depressions, and therefore the position check mark consisting of the mark holes can be measured with high precision. Further, a hole-shaped pattern is overlaid by using a hole-shaped mark, and an influence of coma aberration can be reduced to lessen misalignment of the pattern as compared with the case where alignment of the hole-shaped pattern is made by using the line-shaped mark.
In the semiconductor device of the tenth aspect of the present invention, since the position check mark has a recess region in which a predetermined region of the interlayer insulating film is recessed, a plurality of mark holes so formed as to penetrate the interlayer insulating film in the recess region and a conductive protrusion plug formed so that its end portion on a side opposite to the semiconductor substrate may protrude from the plurality of mark holes and the barrier metal layer is so formed as to be electrically connected to the protrusion plug, surfaces of the barrier metal layer and the conductive film thereon corresponding to the positions of the mark holes have projections, and therefore the position check mark consisting of the mark holes can be measured with high precision even if the barrier metal and the conductive film are opaque. Further, a hole-shaped pattern is overlaid by using a hole-shaped mark, and an influence of coma aberration can be reduced to lessen misalignment of the pattern as compared with the case where alignment of the hole-shaped pattern is made by using the line-shaped mark.
In the semiconductor device of the eleventh aspect of the present invention, since the opening size of each of a plurality of mark holes ranges from almost as large as that of the contact hole to almost twice, a plurality of mark holes can be filled in the same manner as the contact hole and the position check mark having the same structure as the semiconductor element can be obtained.
In the semiconductor device of the twelfth aspect of the present invention, since a plurality of mark holes are formed through the same process as the contact hole, a manufacturing process is simplified as compared with a case where a dedicated process of forming the mark holes is established.
By the method of manufacturing a semiconductor device of the thirteenth and fourteenth aspects of the present invention, the position check mark in which the second wiring layer is formed along an outline of the mark structure to leave the level difference of the mark structure as the projection and depression of the second wiring layer and therefore the mark structure can be measured indirectly through the second wiring layer can be obtained through the same manufacturing process as the semiconductor element.
By the method of the fifteenth aspect of the present invention, the position check mark having the second interlayer insulating film having an outline with projection and depression corresponding to the outline of the mark structure and the second wiring layer formed along the outline of the second interlayer insulating film, in which the level difference of the mark structure is left as the level difference in projection and depression of the second interlayer insulating film and further as the level difference in projection and depression of the second wiring layer and therefore the mark structure can be measured indirectly through the second wiring layer can be obtained through the same manufacturing process as the semiconductor element.
By the method of the sixteenth aspect of the present invention, the position check mark in which a surface of the barrier metal has depressions corresponding to the positions of the mark holes and further the conductive film thereon has depressions and therefore the position check mark consisting of the mark holes can be measured with high precision can be obtained through the same manufacturing process as the semiconductor element.
By the method of the seventeenth aspect of the present invention, the position check mark in which surfaces of the barrier metal and the conductive film thereon have projections corresponding to the positions of the mark holes and therefore the position check mark consisting of the mark holes can be measured with high precision can be obtained through the same manufacturing process as the semiconductor element.
In the method of the eighteenth aspect of the present invention, by setting the opening size of each of a plurality of mark holes from almost as large as that of said contact hole to almost twice, a plurality of mark holes can be filled in the same manner as the contact hole and the position check mark having the same structure as the semiconductor element can be obtained.
In the method of the nineteenth aspect of the present invention, since the interlayer insulating film is planarized by CMP, the interlayer insulating film can be planarized with high precision and downsizing of the semiconductor device is facilitated.
An object of the present invention is to provide a semiconductor device which allows a reliable measurement of an alignment mark and an overlay check mark with high precision in a lithography process and avoids formation of unnecessary structure for mark, suppressing creation of extraneous matters, to prevent deterioration in manufacturing process yield, and a method of manufacturing the same.